ADLINK's PCI/PCIe-7300A and cPCI-7300 are ultra-highspeed digital I/O card consisting of 32 digital input/output channels. High performance designs and state-of-the-art technology make these cards ideal for a wide range of applications, such as high-speed data transfer, digital pattern generation and digital pattern capture applications, and logic analyzer applications. Trigger signals are available to start the data acquisition of pattern generation.
■ Maximum Data Acquisition Rate
For sustained data transfer directly from or to host memory, the maximum data acquisition rate can be 80 MB/s. The maximum data transfer rates between external device and onboard FIFO can be up to 80 MB/s for DO and 160 MB/s for DI. 80MB/s is achieved by 32-bit data width multiplied by an internal 20 MHz clock. 160 MB/s is achieved by 32-bit data width with an external 40 MHz clock for digital input channels only. The PCI/PCIe-7300A, cPCI-7300 can reach 160 MB/s throughput only when the acquired data length is less than FIFO size (16 k samples).
■ Bus Mastering DMA
The PCI/PCIe-7300A, cPCI-7300 performs high-speed data transfers between onboard FIFO and host memory using bus mastering DMA and scatter gather. When the PCI/PCIe-7300A, cPCI-7300 becomes the bus master, it takes control of the PCI/PCIe/cPCI bus, transfers data at burst speed, and then releases the bus. The host memory can be utilized as much as possible to store data when the data acquisition throughput is less than the sustained PCI bus bandwidth.
■ Scatter Gather Support
For bus master devices, the hardware has the special-design built-in support for transferring data to and from non-contiguous ranges of physical memory. The PCI/PCIe-7300A, cPCI-7300 contains multiple pairs of address and length registers, each one describing a single contiguous buffer segment. This allows the PCI/PCIe-7300A, cPCI-7300 to perform I/O using buffers that are scattered throughout DMA address space. These multiple address and count registers are often referred to as a scatter/gather list, and you can also think of these bus masters as having their own built-in mapping registers. With scatter gather support, the data transfer size is no longer a limitation, and moreover, ring buffer is easily achieved with the link list of the scattered memory.
■ I/O Port Configurations
The PCI/PCIe-7300A, cPCI-7300 is initially configured as two ports: PORT A and PORT B. Each port controls 16 digital I/O lines. The I/O ports can be configured as either input or output. According to outside device environment, the PCI/PCIe-7300A, cPCI-7300 can be configured to meet all high-speed digital I/O data transferring. PCI/PCIe-7300A, cPCI-7300 can support many different digital I/O operation modes:
- Internal clock: The digital input and output operations are handled by internal clock and data is transferred by busmastering DMA.
- External clock: The digital input and output operations are handled by external In/Out strobe signals (DI_REQ or DO_ACK) and data is transferred by busmastering DMA.
- Handshaking: Through REQ and ACK signals, the digital I/O data can have simple handshaking data transfer to guarantee no data loss.
- Pattern generation: The PCI/PCIe-7300A, cPCI-7300 reads or writes digital data at a prede termined rate. Users can control the rate internally via by onboard counters with 50 ns timing resolution.
